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Detailed hardware modification for adding a DPDT switch to the Cheetah 64K RAM pack, allowing the 8-16K address block to be disabled so incompatible ROM cartridges (e.g., word processor modules) can be used simultaneously. Requires cutting two PCB traces (from IC4 pin 14 to the ROMCS edge connector and from IC4 pin 14 to IC3 pin 12) and soldering four switch wires plus two jumpers. Works by blanking the column address strobe (CAS) for the 0-16K dynamic RAM refresh cycle when switched out.