Paul Hunter‘s comments on using 450ns EPROMs on ZX/TS computers (May83) strike me as true but incomplete. Paul shows how to add a flip-flop to delay the computer by inserting wait states and thus make the computer read slow EPROMS. You can use another chip select scheme to cure access problems without adding circuitry or slowing down your computer.
Hunter correctly points out the increased circuit propagation delays. The maximum delay from address set-up to output on the LS139 is 27ns, according to Fairchild’s TTL data book. The maximum delay from ENABLE NOT to output is 24ns. From this, we can say while the 27 or 24ns delay of one device may not cause speed problems, if we cascade two halves of an LS139, we get a maximum of 54ns delay–much too long for high speed computers such as ZX/TS.
Every designer must partially solve this problem by avoiding cascading (connecting in series) LSI integrated circuits such as the 74LS139. So–don’t cascade! Use a 74LS138 instead of 74LS139s, and do it all at once. The delays through the LS139 equal those in the LS138, but we avoid a cascade; it’s a 3-to-8 decoder, not 2-to-4.
Hunter did not consider the RC delay, composed of the 470-Ohm resistors in the ZX/TS data lines and the capacitance of the Z80 CPU and ULA chip data pins. Without knowing the data pin capacitance, you can’t compute the delays this network causes data going to the CPU. But you’ll get 5ns delay for each 10pF of input capacitance.
I experience no access problems with the 2716 reader from SQ, using 450ns EPROMS. My board works without fail on my ZX80 with 450ns 2716s, even with the buffer circuit shown in SQ causing additional delays to all signals.
But I did run into the problem on my 2764 reader (to appear in a future SQ). There, I solved the problem on a design level.
Rather than paying the price of extra wait states and hardware, thus slowing the computer, we can change the way we decode and pay with more current drain.
According to the AMD2716 data sheet, the access time from CE NOT (pin 18) to valid data is 450ns. The time from address lines stable to valid data is 450ns. AND THE TIME FROM OE NOT (pin 20) TO VALID DATA IS 120ns! If we ground the CE NOT pin, and connect the output of our decoding circuitry to OE NOT alone, then the EPROM access time is 450ns after the address lines are stable. This brings the 450ns EPROM’s access time well within the correct range for a Z80 running at 3.25 Mhz. You won’t find any speed problems connecting the EPROM this way, the fastest way to operate it.
Current drawn by the EPROM almost doubles, because the CE NOT input is also the POWER DOWN pin. If always selected, the EPROM never powers down, using more current.
If we tie the CE NOT input to the RD NOT output from the Z80, the access time becomes 450ns after RD NOT goes active. If connected this way, you could say that ALL delays from our decoding circuitry become cancelled, since the 120ns response from the OE NOT is so fast that the delays play no role. Now the chip powers down whenever RD NOT goes inactive (high).
I use this approach on my 2764 reader circuit, and recommend it to solve access problems you may run into on my 2716 reader. Implement it easily on the reader by removing the feedthrough near pin 18 on each EPROM socket, jumpering all 4 pin 18s together, and then tying this to pin 3 of U1 (RD NOT). Current drawn by these EPROMS increases about 15mA each.