ACKNOWLEDGEMENTS:
Toni Baker’s book “Mastering Machine Code On Your ZX/81” was a big help in disassembling the ROM code and printing it out.
Dr. Ian logan’s & Dr. Frank O’Hara’s book, “The Complete Timex TS 1000 / Sinclair ZX 81 ROM Disassembly” was a big help in understanding what I had printed out.
National Semiconductor’s “TTL Data Book” made it possible to select the standard ICs for drawing the simulation circuits.
Zilog’s Technical Manual on the Z-80 Microprocessor was very helpful, in this study, as to timing.
Time Designs Magazine for clairifying some points pertaining to the I/O section and the Frame sync timing.
There are many others who have added to my knowledge and understanding.
I wish to thank one and all for their many contributions.
The History and The Problem:
Early in 1982, I believe in either February or March,I bought my first TS-1000 computer. At the time, I was building my own computer based on the S-100 bus using the Z-80 microprocessor as the CPU. I bought the TS-1000 intending to use it to write the ROM and Character Generator for the computer that I was building.
When I plugged it in and tried it out I discovered that the little TS-1000 with a 16K RAM pack would do a lot more than the computer that I was building. The whole TS-1000 system cost less than what I had spent building one 8K RAM board and the power that it used was next to nothing. Needless to say, my S-100 computer construction stopped the day I bought the TS-1000.
Now I have seven computers and four of them are Timex / Sinclair computers. All of the Sinclair computers are excellent computers and with the proper peripherals they will measure up to anything on the market in the microcomputer field. These computers are also very portable. Since 1940 I have worked and played with computers, Mainframes, Minnies and micros. We have come a long way since the old 6SN7 flip-flops.
Now for the problem part. It is my opinion that in order to get maximum utility from any device you need to know exactly how it works. Since the day I bought my first TS-1000 to the present, I have read everything I could get my hands on trying to obtain an accurate understanding of the Sinclair Logic Chip. There are many viewpoints and different opinions about the functions of this chip.
On April 7, 1988 I decided to use the ROM routines to try and discover just what the SCL does and how it does it. The following is the result of that attempt. There may be some errors or oversights or misconceptions. If anyone wishes to comment pro or con or has questions or something to add feel free to write me. If you desire a return letter, please include a SASE. My address is: DONALD B. LAMEN, [address omitted], WINDSOR, NEW YORK .
THE RESULTS
Prime Clue In Timing:
While running the display routines on paper, keeping tract of the timing in microprocessor T cycles, I discovered that each character row scan line takes 207 T cycles. This the key to the entire timing chain.
Taking 207 T cycles as the length of each scan line (including sync and retrace) and going through the entire display routines (including frame sync) I was able to resolve the length of the horizontal sync pulse. The horizontal syncpulse takes 19 microprocessor T cycles.
To understand the Logic Chip we must remember that it is timed by the Dot Clock which is twice as fast as the Microprocessor Clock. Therefore, one scan line is 414 Dot Cycles, the horizontal sync is 38 Dot Cycles, etc..
The SCL Chip:
The SCL Chip is a Mask Programable Universal Logic Array (ULA 2C184E ) made by Ferranti in Italy. This chip is programed at the time of manufacture by Photo-Masked deposition according to a table prepared by the equipment manufacturer (Sinclair). The SCL Chip provides the following functions and/or circuits:
a) Dot Oscillator and Internal Clock
b) Microprocessor Clock
c) Internal Timing Chain
d) Horizontal Sync Generator
e) Character Scan Line Counter_3 bit
f) Internal Data Bus
g) Intercept Control Circuit
h) Internal Data Latch
i) No-Op Generator
j) Two Shift-Registers_8 bit, each
k) Input I/O Port FE_7 bit
l) ROM-Driver Buffer_9 bit
m) I/O Decoder
n) NMI Generator
o) Frame (Vertical) Sync Generator
p) Video Combiner and Inverter Circuit
q) ROM/RAM Select Circuit
The purposed function diagram of the ULA 2C184E chip (SCL) goes here.
DESCRIPTIONS OF THE FUNCTIONS
Dot Oscillator:
The Dot Frequency is controlled and stablized by a 6.5 MHz ceramic filter used as a crystal in a series resonant circuit. A circuit external to the SCL chip. There is also a series capacitor and a shunt resistor in this circuit.
Refering to the simulation circuit presented further on, the resistor R1 being across the crystal and the capacitor C1 will lower the Q of the circuit broadening the resonance. This helps mask any jitter caused by switching within the chip. Also R1 in conjunction with R2 sets the bias and operating point of the transistor. C3 and C4 being across the filter tends to lower the frequency of oscillation while C1 tends to increase the frequency. The ratio of C3 to C4 determines the amount of feedback.
Microprocessor Clock:
The Microprocessor Clock is the Dot Frequency divided by two (3.25 MHz) and inverted. This may be generated by a single flip-flop using the Dot Clock both as a clock and as an input. However, it is probably taken from the first stage of the timing chain counters. External to the SCL chip is a circuit built around transistor TR2 which buffers the Processor Clock and re-inverts it.
Internal Timing Chain:
The Internal Timing Chain must provide the following functions:
a) Divide the Dot Clock by two to provide the Processor Clock signal.
b) Provide Turn-On and Turn-Off pulses to the Horizontal Sync Flip-Flop, to generate the Horizontal Sync pulses with a duration of 38 Dot cycles, at the begining of each TV scan line.
c) Provide a four bit binary counter (divide by 16). The first three bits of this counter provides the timing for the Intercept Circuit and the first bit may also furnish the signal for the Processor Clock, which would then be inverted and sent to Pin 14. The forth bit is used to multiplex the two Shift-Registers. The counter’s Carry-Out(Overflow) enables the next counter in the string for ONE count.
d) Provide a second five bit binary counter (divide by 32). By presetting the first counter to the value of 2 and this secound counter to the value of 6 and NANDing bit 4 of the first counter with bit 4 of the second counter we obtain our Turn-Off pulse for the Horizontal Sync Generator. The Carry-Out of this second counter provides the Horizontal Sync Turn-On pulse terminating the scan line. This Carry-Out pulse also advances the Character Scan Line Counter and presets the Main Timing Chain, thereby starting the next scan line of 414 Dot cycles. (In the simulation two 4 bit counters are substituted for the 5 bit counter with the Carry-Out of the second counter enabling the third counter and the third counter’s Carry-Out taking care of the termination chores. The third counter is preset to 14.)
Horizontal Sync Generator:
The Horizontal Sync Generator is basically a flip-flop which is turned on and off by the Main Timing Chain. The Output of the Horizontal Sync Generator supplies the Horizontal Sync Pulse to the Video Combiner Circuit. It also supplies the source signal for the NMI Generator and one of the control signals for the Intercept Circuit. These pulses are 38 Dot cycles long and come from the Q output of the flip-flop.
Character Scan Line Counter:
The Character Scan Line Counter is a 3 bit binary counter (A 4 bit counter is shown in the simulation, but only the first 3 bits are used ). This counter is reset by a reset signal which is generated by the Frame Sync Generator and is held in the reset mode until the end of the Frame Sync Pulse. This is necessary because the number of Dot cycles in a scan line is not evenly divisible by eight (the number of scan lines in a character row) and holding the reset affords a method of resyncronizing the counter. The counter is advanced one count at the completion of each scan line. The output of Bits 1 to 3 (count from 0 to 7) is fed through the first 3 bits of the ROM Driver Buffer (a 9 bit tri-state buffer) to Address Lines A0′ to A2′.
Internal Data Bus:
There is an Internal Data Bus connected to D0 through D7 (8 lines), which carries data to and/or from the following:
a) Internal Data Latch
b) NoOp Generator
c) Two Shift-Registers_8 bit each
d) Input Port FE_7 bit
e) Lines D6 & D7 to Intercept Control
Intercept Control Circuit:
The Intercept Control Circuit controls the flow of signals on the Internal Data Bus and Screen Inversion. It’s Timing and Control signals come from the following sources:
a) The first counter of the Main Timing Chain
b) A15
c) M1
d) The Horizontal Sync Generator
e) HALT
f) D6
g) D7
Note: M1 in item (c) and HALT in item (e) should both be over-lined.
The timing counter bits are weighted as follows:
Bit-1 _____ 1
Bit-2 _____ 2
Bit-3 _____ 4
Bit-4 _____ 8
The Intercept Control Circuit consists of the following circuits and/or components:
a) 6 Timing Decoders
1. Multiplex Timing (Code 8 or Code NOT 8)
2. Sensing (Code positive edge of 2 AND NOT 4)
3. Latch-In (Code 1 AND 2 AND NOT 4)
4. No-Op (Code NOT 2 AND 4)
5. Latch-Out (Code 2 AND 4) inverted
6. Load (Code 1 AND 2 AND 4)
b) 3 Flip-Flops
1. Intercept Flip-Flop
2. Inverse Flip-Flop 1
3. Inverse Flip-Flop 2
c) 3 Reset Gates
1. Intercept Reset Gate
2. Inverse Reset Gate 1
3. Inverse Reset Gate 2
d) 2 Multiplexed Clock Gates
1. Inverse Clock Gate 1
2. Inverse Clock Gate 2
e) 1 Iverse OR Gate
f) 2 Multiplexed Shift-Register Load Gates (1&2)
g) 6 Inverters
The Intercept Control Circuit works as follows:
The timing of this circuit is controlled by the first counter of the Main Timing Chain, which counts from 0 to 15 overand over except when preset. When preset to 2 it counts from 3 to 15 then goes to 0 (14 counts). Each time this counter returns to 0 it puts out a Carry-Out to the next counter.
On the rising edge the counter’s T-cycle 0 (Code NOT 8) the Shift-Registers are switched and Shift-Register 1 becomes inhibited. On the rising edge of the counter’s T-cycle 8 (Code8) the Shift-Registers are switched back, Shift-Register 2 becoming inhibited. The Uninhibited Register now shifts out it’s eight bits of data to the Video Combinor.
The inhibit signal is delayed for about a half a Dot cycle the active shift-register time to shift out it’s last bit.
The NOT M1 signal is Inverted and ANDed with the signal on A15 then fed to the ‘D’ input of the Intercept Flip-Flop. At the rising edge of Dot-Cycle 2, of the character set of 8 Dot cycles, (Code 2 AND NOT 4) the signal on the ‘D’ input is clocked in. If NOT M1=0 AND A15=1 the Intercept Flip-Flop is SET otherwise it is RESET. SETing the Intercept Flip-Flop enables the rest of the timing gates, except for MUX which is always enabled.
During Dot cycle 3 (Code 1 AND 2 AND NOT 4) the data on the Data Bus lines D0 through D5 will be latched into the Internal Latch and the contents of D7 will be clocked into Inverse Flip-Flop 1 if Code NOT 8 or into Inverse Flip-Flop 2 if Code 8. However, if D6=1 (or NOT HALT=0 or during Horizontal Sync), then the Intercept Flip-Flop will reset, disabling the intercept and allowing the Z80 to read the HALT instruction as usual.
During Dot cycles 4 & 5 (Code NOT 2 AND 4) the No-Op Generator is enabled forcing all eight Data lines to 0. The Z80 reads the No-Op instruction and fetches the next byte from the memory.
During Dot cycles 6 & 7 (Code 2 AND 4), while the Z80 is decoding the No-Op instruction and refreshing the memory, the Intercept Circuit enables the Tri-state Output Buffer (ROM Driver), putting the Output of the Character Scan Line Counter on Address Lines A0′ through A2′ and the Latched Data (Character Code) on Address Lines A3′ through A8′. At the same time the Address Lines A9 through A15 contains a copy of the contents of the I Register. This accesses the Dot Code from the ROM, which the ROM places on the Data Bus.
During Dot cycle 7 the 8 bit Dot Code on the Data Bus is Loaded into the inhibited Shift-Register.
During Dot cycle 8 the Shift-Registers are switched and the same operations are repeated, but on the opposite Shift-Register.