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Part III
Before discussing the roll of the SCLD in bank switching, it is desirable to summarize the known functions.
1. Screen Maintenance
This is the highest priority operation. The HOME RAM with addresses in chunks 2 & 3 (DRAM) belongs to the SCLD. The CPU has to beg permission to access it. If access is not granted, when the SCLD is busy, the CPU clock signal is frozen high, putting the CPU in a state of suspended animation.
There are three screen operating modes. At start-up D_FILE1 & A_FILE1 are used to create the screen display. There are 256 pixels per active screen line. INK and PAPER colors are defined for 8×8 pixel character space.
In extended color mode, there are still 256 pixels across the screen, but now D_FILE2 is used to provide INK and PAPER colors for each 1×8 space. Neither A_FILE1 nor A_FILE2 is used, making the space available for other purposes.
BRIGHT and FLASH are also specified in addition to color for these two modes.
In 64 column mode D_FILE1 and D_FILE2 are combined to double the horizontal resoluton to 512 pixels per line. In this mode the INK, PAPER, and BORDER colors are fixed for the entire display.
Dual screen mode is the same as normal, except you have the choice of using D_FILE1 and A_FILE1 or D_FILE2 and A_FILE2.
The display mode code and 64 column mode color selection are stored in the lower six bits of the read/write register at port address 255. The BORDER color is write-only to the lower three bits at port address 254. The SCLD does the port address decoding and maintains these two registers.
2. Keyboard Monitoring
A read-only register is maintained at port 254. Though all 16 bits of adress are required, only trhe lower eight are decoded. Keyboard data are read from the lower five bits.
3. Tape Input Monitoring
Bit 6 of the read-only register at port 254 is assigned to this function.
4. Tape Output and Beep
Bits 3 and 4 of the write-only register at port 254 are assigned to a two-bit digital-to-analog converter. With bit 4 off, bit 3 generates the tape signal at too low a level to overcome the bias to the speaker circuits. Toggling bit 4 generates beeps.
If bit 3 happens to be low, some 2068s suffer loss of sound. OUT 254,255 should fix this. (White border)
5. Sound and Joystick Operations
In this case the SCLD supports no registers but does decode port addresses 245 and 246 to a pair of signal lines. With both lines active, the port 245 write-only steering register (4 bits) is enabled. When only one or the other line is active, a read or write is enabled for the selected register between CPU and PSG through port 246. Though the I/O “A” register is one of these, it is configured as an input or output port to the joystick connectors. When in input mode, it cannot be written.
6. Keyboard Interrrupt Generation
Immediately after completing a display frame, the SCLD issues an interrupt (also supplying a pull-up resistor) to the CPU. It can be blocked by writing a “1” to bit 6 of port 255 without disabling interrupts from other sources.
7. Local Memory Suppression
Local memory consists of the HOME RAM, EXROM, and the DOCK. On receipt of the BE signal, no local memory is enabled. This is required when EXBU banks 1 through 253 are established and actively reside in chunks.
8. Home Memory Selection
The SCLD decodes address bits A14 and A15 to generate four memory enable signals in blocks of two chunks each . Unless address contention exists, this is independent of display generaton. Often two are active simultaneously. (It is possible for the SCLD to redirect the CPU request to a different block of RAM. This has subtle implications.)
9. EXROM and Dock Bank Switching
Bit 7 of port 255 is a steering bit. When set, EXROM will be found, otherwise the DOCK bank. The SCLD decodes port address 244 and maintains a read-write register called “horizontal select” (HS). Its bits correspond to chunks. A bit set to “1” means that a CPU request to that chunk will find EXROM or DOCK instead of HOME memory.
The two are mutually exclusive. You cannot have EXROM in one chunk and the DOCK in another.
This limited part of the bank switching system works—up to a point. It is difficult to address EXROM or DOCK above chunk 1.
Added memory, except EXROM and DOCK in chunks 0 and 1, is not selected by the SCLD. You must provide the chunk address decoding of A13 thru A15; and multiplexing if needed for dynamic memory.
10. Contention Resolution
While the SCLD is busy with screen maintenance, it operates an independent DRAM data and multiplexed address bus at high speed in a special way. When not busy, a CPU request for DRAM access is honored by issuing signals which open address and data gates between the CPU and SCLD busses. The data gate is bidirectional but the address gate is one-way.
Contention also exists when the CPU requests access to any or the SCLD ports. This is why the design of “hyperloaders” must take into account the fact that the tape signal cannot be sampled more than 15,750 times a second. This resolution limits the amount of tape speed error permissible during all tape operations.
11. Home Memory Multiplexing & Refresh
The SCLD provides this service for the CPU concurrent with screen maintenance except during contention. It also provides A7R to help in external multiplexing.
This includes all the SCLD functions which have been explained adequately if not clearly in the literature.
Is it possible to discover its other secrets without a map? Shades of Sherlock Holmes—let’s have a go at it. What evidence do we have?
There is physical evidence. Much of it has little to do with bank switching, but should not be prejudged.
- The 2068 contains a “daughterboard”. The schematic has an error. The bus connection is to MREQ, not WR as shown. It also shows jumpers G-G and H-H. These are actually cut-and-jump locations. There are no terminals. The function of this board is to remove contention when chunks 2 and 3 have been bank switched and no longer contain HOME RAM. The cut-and-jump locations become important when BUSREQ acts to take over the system bus.
- The rear connector pads for DZIN, DZOUT, BUSISO, and one unassigned connection are not designed for internal wiring. The pads have no traces, holes, nor free area to take solder, so…
- These signals must be provided by an external device.
- The signals are not needed internally.
- The connection marked IOA5 is shown connected to the wrong pin. This can cause confusion when reading or writing code.
- Neither joystick connector has the ground shown on the schematic, though it can be jumped. This might have been done to reserve a pin for future expansion. It is not hard to pick up this ground connection when devices are added that use the joystick ports. The +5V is present. Pin 5 seems to have been reserved for a joystick with a second button if the schematic notation at the switching voltage regulator means anything.
- Address line A13 is connected to the SCLD! NONE OF THE DESCRIBED FUNCTIONS USE OR NEED IT!
- The pull-up resistor on D2 has a simple task. It acts as a RESET to the 2040 printer while initializing.
- The pull-up resistor values for RESET, BUSREQ, WAIT and NMI represent the number of devices which can be “wire ORed” together on each line. The lower the resistance, the more can be attached. Devices issuing BUSREQ outnumber those issuing WAIT. Only a few devices can issue NMI; commonly very fast devices.
There is a very rich body of evidence in the bank switching and initialization code. Even more exists where TIMEX put in roadblocks in ROM to keep unsupported features from messing up the user. Many of these roadblocks can be removed by replacing them with NOPs, but not everything is that simple. Most of them can be intercepted using ON ERR and the GO TO version of the USR call.
What is important here, is that the roadblocks have interfered with testing how the system works.
At this time, I must digress. The full disclosure of how the TIMEX system works takes so many pages that it would be unfair to have it bump other important articles from publication. It would be equally unfair to stretch it out over time.
I mentioned IEEE 488. There is also the “boxes and boards” method used by the AMIGA, the DAISY CHAIN used by the C64, and for simpler applications with the TS2068. They vary in how much external hardware is needed, but the 2068 protocol makes them all possible.
Part 4 will describe the basic bank switching controller, but implementing it in hardware depends on how far you want to go.
Half the fun is trying to solve the riddle yourself. With that in mind, I give you a starting point. You have already seen a few good clues, but clues do not take the place of active investigation. Some of you will flounder. Others will take this tiger by the tail and twist it.
The 2068 WILL WORK in all three interrupt modes. In IM1 (as initialized) the SCLD provides the only interrrupt—and that is used to interrogate the keyboard. Before we can use most peripheral devices and bank switching, this must change.
At 3382d in the initialization is the code to load the Z80 I register. It is followed by six NOPs to allow any device that might be listening time to digest it. The initial value is 63.
Later, at 3480d, we find IM1 followed by one NOP, partly for the same reason.
Is the SCLD listening? There is an old saying, “TEST. DON’T GUESS.”
If so, entering IM0 would require that an instruction be put on the data bus in response to the CPU interrupt read cycle. If nothing responds, the data bus will be all ones. This is RST 56 which is the correct instruction. It might be necessary to add pull-up resistors for reliable operation.
This is the 8080 compatible interrupt mode. Because the SCLD does not need to do anything different, this test might not tell us anything.
Entering IM2 is a different story. The interrupting device is responsible for providing an interrupt vector with bit 0 = “0”.
If the SCLD does nothing, an invalid odd vector (255) will be read, resulting in a crash.
The Z80 “I” register (value 63) establishes the base of the vector table at 16128—pointing to the character set in ROM. A crash is assured even if the SCLD provides a valid vector.
Changing the value to 94 puts the vector table where it should be: at 5E00h.
A crash is still assured unless we build a table there. For test purposes, all 128 entries should point to the keyboard interrupt routine at 62AE. With this single-minded table, any vector supplied by the SCLD will act the same as in IM1.
If it crashes, the SCLD was not listening, or we did something wrong. Don’t forget to code those six NOPs after loading “I”.
Because of the 15,750 Hz limit on sampling rate (the vector table is in contention space), these interrupt pointers cannot be used for really fast devices.
For high speed, the non-maskable interrupt (NMI) is needed. This requires using an external interrupt manager chip. An alternative is to provide additional vector tables outside of contention space. It is simple to switch tables.
The connection of A13 to the SCLD is explained when we examine the code for WRITE_BS_REG AT 635Ch and READ_BS_REG at 63AD. As far as the CPU can see, WRITE_BS_REG is a multibyte NOP. Though the same cannot be said for READ_BS_REG, both routines leave with RAM and the PSG in their original states.
Now THIS is “doubletalk”. The SCLD is listening during this time for its instructions. How does it respond? It sends signals through the joystick port.
What else does it do? According to published information it just about takes over the computer.
DON’T YOU BELIEVE IT!
TEST. DON’T GUESS.
Part IV will explain the basics of real bank switching, though it cannot give you actual examples of working circuits. As you should be aware by now; bank switching is but one element in the larger task of peripheral management. It is a tool…not an end in itself.
Part IV
It was said that the SCLD outputs signals through IO port “A”. This is a perfect example of a half truth which can totally misdirect an analysis of the true circumstances. It is akin to the text book discussions about the SCLD wresting control from the CPU when in fact it yields it.
In the same way, DZIN and DZOUT are deliberately misleading as labels, though a corporate executive might strongly argue that. In the view that the TS2068 is the BOSS, these labels could have some validity, but only for TIMEX products which were never produced. Such being the case, the entire data published about the TIMEX bank switching controller is:
PURE FICTION!
There might have been one. One could be made to those specifications and protocol, but it would be meeting corporate goals.
DZOUT is bidirectional, as is DZIN. Not only that, neither signal implies daisy chaining. (They are analogous to IFC and NDAC on the GPIB buss.) The direction depends on which device is the current BUSS MASTER. In a network of computers the 2068 might be boss, but more likely it would be an intelligent TEMINAL. As a SLAVE, it will never issue DZOUT, but it will respond by completing current operations and releasing DZIN. When all the slaves have released DZIN, the BOSS that sent DZOUT takes over.
Actually it is more accurate to say it is the bank switching controller rather than the 2068 which provides these features, but “bank switching controller” is another misleading choice of words. “Peripheral Control Adapter” is a much better name…. but lacks the pizazz some would demand. GPIB is close, but…
The 2068 does contain part of a Peripheral Control System. This part is NOT FICTION! It is REAL! It is there to USE!
The SCLD permits, or rejects, reads and writes to any ports or memory under its control. It is not in any way the source of signals to IO port “A”, but it does send interrupt and sync data to whatever CPU might be in control of the buss. A stop-action DEMO program called “Sherlock Holmes” graphically displays this. (External CPUs are not synchronized as is the HOME Z80.)
When the CPU tries to read port “A”, it is sometimes detoured to reading a signal from the SCLD instead. The SCLD pulls data bit 0 low when it is not busy in case the CPU issues a delayed interrupt vector request.
This means the keyboard interrupt vector is 254.
BUSISO is not misleading. It is a local signal; the purpose of which is to prevent interference from the joysticks. There is no way for the joysticks to generate, nor interfere with an all 0’s output on port “A”. For this reason, 0’s output on IOA0 thru IOA3 is a trigger signal to invoke BUSISO.
IOA5 (it really is) has another function. When BUSISO is triggered, it steers control to either of two port “A” devices. The value 0 is assigned in the TS2068 protocol for “mine”. In practice, it is useful as a disable signal for the local controller when another buss master is in charge; though it is just as possible for the external buss master to use the same local controller.
When enabled, the “PCA” receives bytes through port “A” as multiplexed “nibbles”. It also receives control signals over address lines A13 to A15. This is the existing system. Beyond that, you can build as elegant a system as you wish. This lets you build systems even more powerful than IEEE488. Bank switching is a typical add-on. It is best to use the bank switching protocol already established in the 2068 RAM code, but it can be changed if you want.
A small system with the 2068 being the BOSS is capable of up to 12 megabytes of memory. This is 253 banks of 7 switch-able chunks of 8192 bytes each. (Actually, it is unlimited when you define “superbanks”.)
Contrary to published information, chunk 3 has the highest priority to be bank switched. It is in contention with DRAM. If not switched out, operations in chunk 3 (and chunk 2) will be a lot slower. (This has been discussed for the Spectrum.) A reconfigured memory assignment using chunk 7 for the stack and the DOCK for SYSCOM could easily be considered standard. Oddly, it seems the bank switching routines were originally written that way before barriers were installed.
A multi-user system could be implemented with each user owning their own personal shadow in chunk7.
Going farther, you can relocate BASIC out of contention space, with parts of it stored in “overlays” from other banks. With proper technique, you don’t have any need for FREE. BASIC can USR call any bank it needs.
PANDORA’S BOX IS OPEN!
LONG LIVE THE 2068! (AND CLONES)
A simple bank switcher latches nibbles, decodes some instructions, buffers an eight bit output buss, and little else. It is the those BEU chips which are the real workhorses. They contain HS, Bank# and Status registers as a minimum. They decode commands, issue BE when addressed, and often contain EPROM data. Whether you want serial or parallel polling, or daisy chaining is your choice. Initially, only 10 EXBUs can be implemented in SYSCON.
There is no stopping the independent development of great new hardware! It would be a mistake to merely adapt programs and hardware designed for the crippled TS2068… not because existing products are not excellent, but because they have had to work in an unfavorable environment. How much more effective it is to start with new goals! Why cling to old compromises? Why waste valuable time adapting?
See the annotated disassembly listing of WRITE_BS_REG for a guide to implementing bank switching.
Though this concludes this series on bank swithching the 2068, the subject has just begun. A book on it could weigh several pounds …far outweighing this publication.
If it has inspired you to not accept a paraplegic TS2068 but to go after what you thought you were buying in the first place, then it has done its job.
WRITE_BS_REG
Enter with Reg D = msb Port Address = Q0 = qqq00000
Enter with Reg E = data byte = BIN YYYYyyyy
AAA
Hex Machine Buss 111 IOA
addr instruction data 543 5 3210 comments
---------------------------------------------------------------
635C PUSH AF F/A 011 x xxxx Save Reg AF on stack
635D PUSH BC C/B 011 x xxxx Save Reg BC on stack
635E PUSH HL L/H 011 x xxxx Save Reg HL on stack
635F LD H,D ** 011 x xxxx
6360 LD L,0 0 011 x xxxx Immediate data
! HL = Q000
6362 LD A,(C000) Y1 *110* x xxxx Get (C000)
6365 PUSH AF Y1 011 x xxxx Save (C000) on stack
6366 LD A,(Q000) Y2 *qqq* x xxxx Get (Q000)
6367 PUSH AF Y2 011 x xxxx Save (Q000) on stack
6368 LD A,7 7 011 x xxxx Immediate data
636A OUT (245),A 7 111 x xxxx Select PSG Reg 7
636C IN A,(246) Y3 111 x xxxx Get (PSG_R7)
636E LD B,A ** 011 x xxxx Store (PSG_R7) in Reg B
636F LD A,14 14 011 x xxxx Immediate data
6371 OUT (245),A 14 111 x xxxx Select PSG Reg 14
6373 IN A,(246) Y4 111 x xxxx Get (PSG_R14)
6375 LD C,A ** 011 x xxxx Store (PSG_R14) in Reg C
6376 LD A,7 7 011 x xxxx Immediate data
6378 OUT (245),A 7 111 x xxxx Select PSG Reg 7
637A LD A,64 64 011 x xxxx Immediate data
637C OUT (246),A 64 111 x xxxx Set Port IOA to OUTPUT
! X XXXX = X XXXX if IOA was OUTPUT
! X XXXX = 0 0000 if IOA was INPUT
637E LD A,14 14 011 X XXXX Immediate data
6380 OUT (245),A 14 111 X XXXX Select PSG Reg 14
6382 XOR A ** 011 X XXXX Zero Reg A
6383 OUT (246),A 0 111 0 0000 Set IOA = 00
! Setting IOA bits 0 to 3 = 0 triggers BUSISO if not on.
6385 LD A,2 2 011 0 0000 Immediate data
6387 LD (C000),A 2 *110* 0 0010 Reset nibble counter
! The SCLD gates buss data to Port IOA on hearing this
638A LD A,E ** 011 0 0010 Get data byte from Reg E
638B LD (Q000),A Y2 *qqq* Y yyyy Write lsn
! Y2 = BIN YYYYyyyy
638C SRA ** 011 Y yyyy Shift right Reg A
638E SRA ** 011 Y yyyy Shift right Reg A
6390 SRA ** 011 Y yyyy Shift right Reg A
6392 SRA ** 011 Y yyyy Shift right Reg A
6394 LD (Q000),A Y2' *qqq* 0 YYYY Write msn
! Y2' = BIN 0000YYYY
6395 LD A,7 7 011 0 YYYY Immediate data
6397 OUT (245),A 7 111 0 YYYY Select PSG Reg 7
6399 LD A,B ** 011 0 YYYY Retrieve Y3
639A OUT (246),A Y3 111 z zzzz Restore Y3 to PSG_R7
! z zzzz = 1 1111 if IOA was INPUT
! z zzzz = X XXXX if IOA was OUTPUT
639C LD A,14 14 011 z zzzz Immediate data
639E OUT (245),A 14 111 z zzzz Select PSG Reg 14
63A0 LD A,C ** 011 z zzzz Retrieve Y4
63A1 OUT (246),A Y4 111 x xxxx Restore Y4 to PSG_R14
! IOA alternate device BUSY can be dropped
63A3 POP AF Y2 011 x xxxx Retrieve Y2
63A4 LD (Q000),A Y2 *qqq* x xxxx Restore Y2 to Q000
63A5 POP AF Y1 011 x xxxx Retrieve Y1
63A6 LD (C000),A Y1 *110* x xxxx Restore Y1 to C000
63A9 POP HL L/H 011 x xxxx Restore HL
63AA POP BC C/B 011 x xxxx Restore BC
63AB POP AF F/A 011 x xxxx Restore AF
63AC RET OPC 011 x xxxx
Addresses *nnn* are memory mapped ports. The SCLD gates the write data to IOA. 011 and 111 are not ports. They correspond to fetches and accesses in chunks 3 and 7. If IOA is INPUT, the operation is ignored.
BUSISO can be triggered with IOA5 = 1. In this event, it is an alternative device of your choice. It is free to have its own rules for dropping BUSISO. It has a lower priority than the bank switching controller (though not limited to bank switching). If IOA5 = 0, the bank switcher is enabled and a BUSY state is seen by the alternate device.