Flicker-free display. 8K ROM required. The SLOW mode upgrade was a small double-sided circuit board that had to be soldered to the ZX80 PCB via several flying leads. In addition, several tracks of the ZX80 PCB had to be cut.
The SLOW mode board works by generating horizontal synchronisation (HSync) pulses during the top and bottom border areas, letting the original ZX80 hardware generate the HSync pulses for the picture area. As with the ZX81, non-maskable interrupts (NMI) are used to count down the number of border lines to output before running the display driver routine in the ROM to generate the picture area or vertical synchronisation (VSync) pulse. It uses a counter that counts 207 clock pulses before resetting back to 0. At a count of 0, a HSync pulse is begun and it will end when the count reaches 20. An NMI generator circuit is switched on during the top and bottom border durations and this circuitry passes the HSync pulses to the ZX80’s video output. When the picture area is being output, the NMI generator is switched off and now the HSync pulses produced by the ZX80 hardware are allowed to pass to the ZX80’s video output. The 3 bit character line counter is held in reset whenever the NMI generator is switched on and released when it is switched off. With the NMI generator off, the character line counter will again be held in reset when a read occurs from input port $FE to start the VSync pulse. The character line counter is released when the VSync pulse ends via a write to any other output port (typically $FF).
