Dueling Devices

Author(s): Paul Donnelly
Publication: Syntax
Pub Details: Syntax/Syntax ZX80 v4 n8 (Volume 4, Issue 8)
Date: August 1983
Pages: 21

Many new peripherals for ZX/TS computers now use I/O addressing. Why? Two main reasons: add-ons already use most “good” memory areas, and even 2K machines can access I/O devices, making them usable without extra memory. This helps reduce costs significantly.

But because I/O manufacturers keep costs low, they must rely on partial decoding of port addresses. Z80 processors can address 256 unique I/O devices (256 inputs and 256 outputs) using lines A0-A7 on the address bus. Each time we fail to use a line to decode, we cut the number of assignable ports in half. For example, if we do not use A7 as part of our device, we can only address 128 unique devices.

 A7  A6  A5  A4  A3  A2  A1  A0
| X | 1 | 1 | 1 | 1 | 1 | 1 | 1 |

(X = not used)

In the above diagram, we show address 127(D), or possibly 255(D), since we don’t use A7. Of course, we must also use IOREQ NOT, and either RD NOT or WR NOT to tell the system we are requesting an I/O port. For any port, we must have at least two lines in our selection logic. To fully decode a port, we need eight more lines, totalling ten. This could require a fairly expensive chip or decoding device.

To cut costs, we only choose a few of the address lines. See the following diagram of two currently available I/O devices.

#1  A7  A6  A5  A4  A3  A2  A1  A0
   | 0 | X | 0 | 0 | X | X | X | X |
Addresses:  0-15d and 64-79d

#2  A7  A6  A5  A4  A3  A2  A1  A0
   | 0 | 0 | 0 | X | X | X | X | X |
Addresses:  0-31d

You can decode these devices cheaply, but they overlap. Problems could develop if you attach both devices at the same time, unless you make sure to use non-overlapping addresses. Clearly, we should not use addresses 0-15 in the example shown. You should select device #1 using the 64-79 area, and device #2 should use a code from 16 to 31.

Decoding schemes for devices #1 and 2 follow. Implementation of this entire decoder in a single 25¢ chip, the 74LS28 Quad OR gate provides one big advantage. But we effectively eliminate a large number of potential addresses–a disadvantage. In both examples, we lose 31 possible ports to get one.

Device #1 decoding gates (IOREQ, RD, A7, A5, A4 to Select #1)
Device #1 decoding gates (IOREQ, RD, A7, A5, A4 to Select #1)
Device #2 decoding gates (IOREQ, RD, A7, A5, A6 to Select #2)
Device #2 decoding gates (IOREQ, RD, A7, A5, A6 to Select #2)

Although keeping costs low by using partial decoding schemes remains important to ZX/TS suppliers and consumers, manufacturers should provide port address ranges in product information and advertising. I suggest you contact vendors before you buy, to determine the compatibility of any new peripheral with those you already own.


Remember that the ZX/TS uses all even port addresses to read the partially decoded keyboard, though it’s always called as 00FEh.–KO