SEPT. 2, 1988
Bill Jones
TS-2068 UP-DATE
1317 Stratford Avenue
Panama City, FL 32404
Dear Bill,
First of all, I would like to comment on your proposed use of both the HOME and DOCK banks for programs simultaneously. The switching between these banks by manipulating bit 7 of the ARSFLG variable @23750 should work as you described. The only known problems in the use of the DOCK bank are those described in paragraphs 6.2 and 6.3.1 of the Timex technical manual and these deal with cartridges which only use machine code. (They are easily corrected by changing the byte @0930H in the EXROM from 40H to 55H and the two bytes @38A0H and 38A4H in the home ROM to 60H and 40H respectively.) I have not analyzed the DOCK bank access routines in detail up to this time because I have not had any problems using the DOCK bank for any of its normal stand-alone functions.
You mentioned power problems with the 2068 and I agree completely that extra loading on the internal power supply should be kept at a minimum. I even went so far as to relocate my LKDOS controller board from the cartridge slot to one of the bus expansion boards at the rear of the computer so that it would be on the external power system. The only extra loading on the internal supply is the 2 chips which were added for proper EXROM address decoding and DOCK/EXROM disabling when an expansion bank is active as described in my last article.
My present bus expansion port plug-ins are lined up as follows:
1. RGB monitor interface and phoneme speech synthesizer. (The external power supply is now connected to this board.)
2. EXROM bank expansion for chunks 1-7.
3. LKDOS controller board.
4. Expansion bank controller board.
5. Port I/O buffer board with real time clock
6. LKDOS disk port board
7. 16 channel A/D board.
8. Text-to-speech board.
9. Digitalker speech synthesizer board.
10. RS-232 interface board.
11. TS 2050 Modem interface.
12. AERCO printer interface.
(You can see that I have been experimenting with several different approaches to speech synthesis for computers.)
Now let me bring you up to date on my progress in developing the expansion bank hardware and software. I have completed the debugging of the EXROM initialization routines. The original Timex protocol was followed in all respects except for the deletion of the routines which reassigned expansion bank numbers according to their interrupt priorities. This was done for several reasons. First, the interrupt service routine address field which is stored in the SYSCON table for each expansion bank is never accessed by any of the existing Timex ROM code. Second, there is no way of currently making use of interrupts from the expansion banks without changing the interrupt mode of the Z-80 processor and if a different interrupt mode were used and the HOME bank then made active, the system would crash. Third, it is unlikely that there would ever be so many expansion banks on line that polling would present an excessive time delay within system routines.
Before I go any further on the system debugging I will refer any interested readers to the excellent 5 part series of articles by Wes Brzozowski entitled “The Mystery of the Missing 253” which appeared in Time Designs Magazine starting with the July/August, 1986 issue. These articles provide a good background description of the ROM routines. These articles actually got me started on the debugging of the system ROM’s.
I completed the debugging of the initialization routines dealing with the ROM (or PROM) based expansion banks over a month ago but the RAM based banks were more of a problem. The RAM based expansion bank initialization routine consists of testing each chunk in the bank for the presence of RAM by means of first writing a test byte, then reading it back and comparing the read back data with the original byte to see if RAM is actually present in that chunk. This test is repeated using two different bytes to verify that there actually is RAM in the chunk and not an accidental match with random garbage read back from an unused address.
The original test routine in the EXROM blithely continued chunk by chunk until chunk 3 was enabled in the expansion bank without bothering to move the O.S.RAM routines from chunk 3 in the home bank to chunk 7 so the system crashed at this point. I added the necessary code to move the O.S. RAM routines to chunk 7 prior to testing chunk 3 in the RAM banks, but the system still crashed. The problem this time was that the routine in the EXROM which moves the O.S.RAM code makes use of data stored in the system variables area which have not been initialized at this point in the overall system initialization sequence. The addition of some code to temporarily initialize these variables solved that problem but we were not out of the woods yet. The system now initialized properly and the SYSCON table was loaded with the correct type of data but the chunk map stored in SYSCON 02 for RAM banks did not show the proper status of chunks 2 and 3 for these banks. Subsequent testing of the write and read-back of memory in these RAM bank chunks indicated that the data was being written in correctly but was read back correctly approximately 10% of the time. Apparently the SCLD chip in the computer was somehow insisting that the home bank should retain control of chunks 2 and 3 since both of these are used for screen display storage. (Chunk 3 is only used for extended display modes.) Attempts to override this control by means of DI software instructions and also by setting bit 6 in port FF proved fruitless. Since the internal architecture of the SCLD chip is unknown, I decided to try the same type of hardware override approach that Timex used when they added the U21 circuit to tristate two of the address and data buffer chips (U5 and U9) when writing to the DOCK bank. The added circuit is shown on one of the enclosed schematics. After adding this circuit which tristates the buffer chips whenever chunks 2 or 3 of either the EXROM bank or expansion banks are active, the SYSCON table was correctly loaded during the initialigation sequence. A copy of the SYSCON table data is enclosed along with a brief description of the function of the entries in the table. The SYSCON 03 through 17 entries for the RAM banks is whatever garbage was in the chunk O RAM at power up. It is unused data for these banks.
I am also enclosing a schematic of a LED display add-on for the expansion bank boards which I found to be very useful to show which chunk in each bank is currently active.
As promised in my last letter to you, I am enclosing an annotated copy of the modified 0.S.RAM routines. Most of the routines have either been corrected or entirely rewritten. The only routine which is not annotated is the DISPATCH routine which serves no useful purpose at the present time. This routine will be the only one which will be entirely deleted if I can come up with some useful routines which will help make use of the expansion banks transparent to the programmer working only in BASIC. This will be one of my next projects now that the debugging of the original Timex code and associated hardware seems to be complete. I want to apologize for the handwritten annotation for this table but much of this was done during extensive business travelling over the past few months. Also enclosed is an updated FIX table for the O.S.RAM code which is used by the code which moves the RAM routines back and forth between chunks 3 and 7 in the home RAM.
During my analysis of the O.S.RAM routines, I originally thought that there was an error in the CALL BANK routine. This routine is used extensively by the tape I/O routines in the original Timex ROM’s, but never with any parameters passed on the stack, either in or out. Detailed analysis of the CALL BANK routine indicated that it is correct as originally written, and the called routine is responsible for cleaning up the stack by deleting the passed parameters after the data has been used by the called routine.
Prior to calling a routine in an expansion bank with parameters passed to the routine, the following items have been stored on the stack in the order indicated:
1. Bytes containing the status of expansion banks. (One byte per bank containing the active chunk map.)
2. Two bytes containing the status of ports F4 and FF.
3. The address inside the CALL BANK routine which will be returned to at the completion of the execution of the code in the expansion bank.
4. The chunk mask and bank number of the called bank.
5. The number of parameters (bytes) to be output to the called routine.
The stack pointer is left pointing to item 3 when the expansion bank is jumped to. I am using the following routine in the expansion bank to recover the stack space utilized by the passed parameters while preserving all Z-80 registers:
F3 DI Disable interrupts.
DDE1 POP IX Save return addr. in IX.
E5 PUSH HL Save HL(overwrite return
address)
C5 PUSH BC Save BC(overwrite chunk
mask and bank number)
210000 LD HL,0 Make HL=SP
39 ADD HL,SP
2B DEC HL Point to high byte of #
of output parameters.
46 LD B,(HL) Get high byte of # of
output parameters.
2B DEC HL Point to low byte of #
of output parameters.
4E LD C,(HL) Get low byte into C
F9 LD SP,HL Assign new SP value.
D5 PUSH DE Save original DE value.
110600 LD DE,6 Offset from SP to start
of parameter list.
19 ADD HL,DE Point HL to parameters.
1100C0 LD DE,C000 Destination address in
bank RAM for storage of
parameters.
EDB0 LDIR Move the parameters from
the stack to the RAM in
the expansion bank.
D1 POP DE Restore DE data.
C1 POP BC Get # of parameters back.
D5 PUSH DE Save DE again.
F5 PUSH AF Save AF.
2B DEC HL Point DE to top address
E5 PUSH HL / in stack where parameters
D1 POP DE / were stored.
A7 AND A Clear carry, if set.
ED42 SBC HL,BC Offset HL by number of
parameter locations.
010800 LD BC,8 8 bytes on stack to be
moved.
EDB8 LDDR Move the stored register
data to recover the stack
space previously occupied
by the parameters.
D5 PUSH DE ] Point SP to start of the
E1 POP HL ] stored register locations
23 INC HL ]
F9 LD SP,HL ]
F1 POP AF Restore original register
D1 POP DE values.
C1 POP BC
E1 POP HL
DDE5 PUSH IX Put the return address on
the stack.
CDxxxx CALL xxxx Call the routine in the
expansion bank which
makes use of the passed
parameters.
FB EI Enable the interrupts.
C9 RET Return to the CALL BANK
routine.I have also developed a routine for loading parameters onto the stack within a called expansion bank routine when the calling routine requires parameters to be input rather than output to the called routine but I will save that for next time.
A brief explanation of the expansion bank hardware operation may be in order. The following refers to the schematics which were published in your last edition. U10, U11, and U18 on the expansion bank controller board are used to buffer the address and data lines which are not already buffered inside the 2068. U19 provides bidirectional buffering of the data to and from the expansion banks. U21, U3, U4, and U7 provide the full port address decoding for either reads of or writes to ports FC and FD. The port FD read function is not utilized at the present time. U17 latches the 3 high order data bits that are transmitted from the computer when a port FD WRITE command is executed. The latched data is then decoded by U13 into a one-of-eight outputs for selection of the appropriate expansion bank port commands.
The subsequent write to or read from port FC will utilize the latched U13 output to determine the function being executed. For example, a read from expansion bank port 40H will be the low nybble of the currently selected banks chunk mask. The bank was selected by sending the bank number to U2 via a write to port 80H. U1 decodes the output of U2 to select one of the 15 possible banks. U15 is used to deselect all chunks in all expansion banks either during a power up reset or by writing a 0 to port C0H. U14 is used as a controlled deselect of chunks common to all expansion banks when a specific chunk is to be reassigned to a new bank. (This is done by the BANK ENABLE routine in the home bank RAM.) The rest of the logic on the controller board is straightforward combinatorial logic to select the required control functions.
Proceeding to the schematic for the individual expansion bank boards, we see that U6 is used for selection of the appropriate chunk selection when memory read/write is active. The memory chips on the board will only be enabled if the specific chunk was previously assigned to the bank. This is determined by the state of the U3, U4, U9, and U10 registers. They are clocked by a write to expansion bank port 40H of the required chunk mask which is presented to the D input pins of the registers. The clear pins are directly driven by the chunk deselect outputs of U14 on the controller board. U1 is used to determine the status of the bank. Bit 2 is read back as a low to verify that a bank is really present when testing for banks during the system initialization. Bit 3 is used (via U8) to determine whether any chunks in the system chunk mask are currently assigned to this bank. A low indicates that one or more chunks are active in this bank and a high read back indicates that no chunks are currently assigned to the bank. U12 is used to pull the BUSISO line low whenever a chunk in the bank is actually being read or written to.
This is a quick summary of overall circuit operation. I’m sure there will be questions from your readers so we will try to answer them in future articles. Now that the basic system hardware and software are in place, the big job remaining is to develop useful software for the ROM expansion banks and available space in the home bank to make use of the expanded memory. Some of your readers that are familiar with the home ROM code may be able to help out on this proect.
One last item for this time. I am enclosing a disk containing the clock setting and reading routines for the circuit which was shown in the last article. You can list them out on whatever printer you prefer. Next time we will start out with a listing of the debugged home ROM code.
sincerely,
Charles G. (Chuck) Bothner
Note: For those readers who have a need, UPDATE will supply the two missing items: 1. Copy of disk mentioned, Oliger or Larken format- $5.00 for postage and handling. 2. 26 page code listing starting at SYSCON 5EEA hex through 683F hex.- $8.00. (ed.)