The ZX80/81 Video Display System
Introduction
In this issue I will discuss the ZX80/81’s display system. As this is a very involved technical subject, let us review how a television picture is generated.
The main element in a television is the CRT (Cathode Ray Tube). A basic CRT is shown in Figure 1. The tube, made of glass, is pumped free of air, creating a vacuum. Electrons are generated at the rear of the tube and shot forward toward the phosphor-cover of the screen. When these electrons hit the phosphor, it turns white. Varying the number (i.e., the intensity) of electrons shot at the phosphor changes the level of grey obtained.
If no other elements were involved, you would simply get a spot at an arbitrary place on the screen. To move the beam of electrons to different parts of the screen, deflector yokes are used. These are coils of wire that create a magnetic field. Circuitry in the TV causes the beam to move across the screen horizontally. When it reaches the extreme right of the screen, a pulse is applied to the system’s control circuitry. This pulse, called horizontal sync, causes the beam to move back to the left side of the screen. As it moves back, it also moves down one scan line. This action is shown in Figure 2. When the beam reaches the bottom right hand corner of the screen, another pulse is applied to the system’s internal circuitry. This signal, known as vertical sync, causes the beam to travel back to the top of the screen. A horizontal sync pulse, applied at about the same time, causes it to travel back to the left. The scanning process then repeats. The time that the beam spends returning, either to the left side or to the top of the screen, is known as retrace time. During this time, no electrons are shot at the screen; thus the name: blanking.
In the United States, a frame is scanned about every 16 ms (milliseconds, thousandths of a second). Thus, the frame rate of 60 Hz is established; the TV receives vertical sync 60 times per second. Horizontal sync is established at approximately 15 KHz (i.e., 15 thousand pulses per second).
The Display
The ZX80/81 video display is created almost entirely by software. All sync (vertical and horizontal) is generated by I/O instructions in the display routine. When the system decides that it wants to display a frame on the screen, it follows these simple steps:
1) Load the HL register pair with the address of the display file.
2) Set bit 7 in H to a 1.
3) Load the R register with a time-out constant.
4) Jump to the address supplied in the HL register pair.
The designer of the ZX80/81 display system decided to use the Z80 microprocessor not only as a processing element to execute programs, but also as a fully software-programmable piece of logic.
The organization of the display file, shown below in Figure 3, was very carefully chosen. When the system ‘jumps’ to the display file, the PC (Program Counter) is used to step through the sequence of characters to be sent out as video. The R (Refresh) register is used to keep track of the timing for the display. The Z80 processor automatically decrements it after fetching each instruction. Address line 6 is connected to the INT (Maskable-Interrupt) line. This means that whenever the A6 goes low (i.e., d6 of R=0) and Interrupts are enabled, the processor is interrupted from executing its present task. Interrupts are enabled only during the time that the system is displaying, so as to disallow spurious interrupts.
Let us follow through the display of a frame on the screen. The system first performs a read of the keyboard port (port FE hex, i.e., A0=low). This causes RD, IORQ, and A0 to become low. This, in turn, causes a set/reset type flip-flop to be set. The output of this flip-flop, sent through a ripple-through arrangement of preset/clear D-type flip-flops, becomes the SYNC signal. This SYNC flip-flop is reset by a write to any I/O port. It is also pulsed by any I/O request (IORQ=0). The display routine is also indirectly responsible for the keyboard scanning. After performing calculations on the data obtained through the initial IN instruction, it writes to an I/O port, ending Frame Sync. Frame Sync lasts for approximately 388µs (1262 T-States; a T-State’s a system clock cycle, and it lasts for 307ns). The system then executes the jump to the display file. In the ULA (Undedicated Logic Array) on the ZX81, the fact that the processor is executing instructions at an area in “memory” whose address has A15 set (i.e., high) is detected. This important control signal is designated DISP.
Reviewing the system’s schematic, you will notice that the data bus is “split” into two distinctly separate buses with eight resistors. These buses are specified as D0-D7 and D0′-D7′. The D0-D7 side of the resistors is connected directly to the Z80’s data bus pins.
When the DISP signal is active and M1 (Instruction Fetch) is active and D6′ is low, a set of eight open collector inverters drives a 00 hex onto the D0-D7 bus. This is the machine code for the Z80’s NOP (No OPeration) instruction. As the processor steps through the display file, it receives NOPs and executes them.
Meanwhile, the actual characters in the display file are sent out from RAM (Random Access Memory) onto the D0′-D7′ bus. They travel through a buffer hatch and into one side of a set of multiplexors. The general configuration of the MUXs is shown in Figure 4. (A multiplexor is a handy piece of logic used to select, as output, one of two inputs. A select line, designated SEL, is used to choose between the two inputs.)
During the execution phase of each instruction, the Z80 performs a refresh: the RFSH line becomes active, the R register goes out on A0-A7, and the I register goes out on A8-A15. The ZX80/81 ROM holds the character generator (map of the characters). Each character is set up as an 8×8 matrix.
As each refresh cycle executes, the character code, combined with the current row address (0 . . . 7) from the three-bit row counter (incremented by Horizontal SYNC), goes to the ROM as the lower nine bits of its address. The rest of the address for the ROM comes directly from the Z80 (i.e., the I register, as this is a RFSH cycle). Thus the I register serves to hold the base address for the character generator which resides in the last 512 bytes of the ROM (4K or 8K).
The eight bits of pixel data come out of the ROM and travel along the D0′-D7′ data bus and into a shift register. The output of this shift-register, clocked at 6.5 MHz, combined with the SYNC pulse, is video.
Earlier it was noted that D6′ was required to be low for a NOP to be forced onto the bus. The code for the NEWLINE line-delimiter in the display file was very carefully chosen to be 76 hex (bit 6=1); 76 hex is a HALT instruction on the Z80. When the system gets to the end of displaying a line of characters, it encounters a NEWLINE character. This instruction is allowed to pass onto the D0-D7 bus and the processor executes the HALT instruction.
All this time, with every instruction cycle, the R register has been decrementing. Its setup value is carefully chosen so as to interrupt the process at the end of each pixel line. The interrupt handler deals with several things. First, the Z80 acknowledges the interrupt with a special “interrupt acknowledge” cycle. This is signified by both M1 and IORQ becoming active (i.e., low). The SYNC flip-flops notice this and cause a SYNC pulse to be sent out to the video-sync combination/modulator circuitry. This pulse is horizontal sync and it lasts for 6.15µs (20 T-States). Next, the “pixel lines left” counter (the C register) is decremented. If the counter becomes zero, then it is reset to 8 (the number of pixel lines per character), and a delay is executed to allow horizontal retrace to occur.
The “lines per frame” counter (the B register), initially 24, is then decremented. If it reaches zero, the frame is done and the display-routine performs a RETurn instruction, permitting the system to continue with the task it was performing before it began scanning the frame.
If either the “pixel lines left” counter or the “lines per frame” counter are non-zero at this point, the R register is reloaded with the proper value, interrupts are reenabled (as the Z80 automatically disabled them when the original interrupt occurred), and a jump is made back into the display file, at the beginning of the same line of characters, so as to scan the next pixel line of the screen.
On the ZX80, constant, “flicker-free” video is not available. This is because, as you can now see, the Z80 microprocessor must be explicitly executing the display loop. On the ZX81, constant video is generated with a bit of additional circuitry. This circuitry is essentially a 60 Hz clock, whose output is connected to the NMI (Non-Maskable Interrupt) line on the Z80. The handler (i.e., the subroutine called when the interrupt occurs) for this interrupt scans a single frame on the TV screen and RETurns, allowing the system to get back to the task at hand, namely, executing your program. When in SLOW mode, interrupts (NMI) are being generated, and your program is being executed only during vertical retrace time: thus the name. Personally, unless I am working with graphics, I prefer the speed.
A Note to Readers
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Until next time, same relativistic time period, same non-Euclidian universe.